Exploring sub-20nm FinFET design with Predictive Technology Models

By S. Sinha, G. Yeric, Vikas Chandra, B. Cline, Yunhui Cao. DAC Design Automation Conference 2012, 2012

325 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/f38b6517389c415542e5a28b1739e38af2c66a34

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In Electrical and Electronic Engineering

1. Bevan M. Baas
2. Aaron Stillmaker

Citations in the corpus

• Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm (2017, methodology): “In a multi-gate transistor, the effective channel width is equal to two times the height of the fin plus the width of the fin, or Weff = 2 × hfin + Wfin [14].”