Experimental determination of the maximum post-process annealing temperature for standard CMOS wafers

By Sherif Sedky, Ann Witvrouw, H. Bender, K. Baert. 2001

164 citations recorded by the source corpus.

Subfields: Atomic and Molecular Physics, and Optics, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/e4bc3cdab7a3171f36716284e75237563512c4be

How researchers see this paper

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In Atomic and Molecular Physics, and Optics

1. Tsu-Jae King

In Electrical and Electronic Engineering

1. Tsu-Jae King
2. C. T. Nguyen

Citations in the corpus

• Polycrystalline silicon-germanium films for integrated microsystems (2003, result): “Since Al with 2% Si was used with no barrier metals, silicides, or plugs, these results do not necessarily indicate how modern transistors might be affected by the MEMS processing [ 34 ].”
• Fully depleted, back-illuminated charge-coupled devices fabricated on high-resistivity silicon (2003, methodology): “Laser annealing is required since the thinning step is performed on a finished wafer and the annealing temperature of the backside implant is limited to 475–525 C depending on the metallization used [26].”