Trading Accuracy for Power with an Underdesigned Multiplier Architecture

By Parag Kulkarni, Puneet Gupta, Milos D. Ercegovac. 2011 24th Internatioal Conference on VLSI Design, 2011

527 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/de03fcfae75c9a571974badcc0584b4ea6400347

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Citations in the corpus

A Survey of Techniques for Approximate Computing (2016, background): “Kulkarniet al. [2011] present the design of an inexact 2x2 multiplier that represents the multiplication of 3 10 ∗ 3 10 with 7 10 , instead of 9 10 .”
A low-power, high-performance approximate multiplier with configurable partial error recovery (2014, methodology): “Proposed multiplier ETM [7] 2× 2 approximate multiplier [6] NMED (%) 0.”
Approximate computing: An emerging paradigm for energy-efficient design (2013, methodology): “In [36], a simplified 2⨉2 multiplier is used as the building block in a larger multiplier for an efficient computation.”
IMPACT: IMPrecise adders for low-power approximate computing (2011, methodology): “A powerefficient multiplier architecture is proposed in [11] which uses a 2 × 2 inaccurate multiplier block resulting from Karnaugh Map simplification.”
DRUM: A Dynamic Range Unbiased Multiplier for approximate applications (2015, methodology): “SSM (m,n) [13] O(m) O(m(2)) m ≥ n/2 Kulkarni (n) [12] O(n(2)) -”
Approximate Computing: A Survey (2016, methodology): “A power-efficient multiplier constructed with 2 2 approximate multiplier blocks was proposed in [52].”
New Metrics for the Reliability of Approximate and Probabilistic Adders (2013, background): “Although not discussed and beyond the scope of this paper, the proposed metrics may also be useful in assessing other arithmetic circuits [20] for inexact computing and/or fault-tolerant designs [21] in nanocomputing applications.”
Accuracy-configurable adder for approximate arithmetic designs (2012, background): “Lu [7] introduces a faster adder which has shorter carry chains and considers only the previous k bits of input in computing a carry bit.”