IMPACT: IMPrecise adders for low-power approximate computing

By Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, Kaushik Roy. IEEE/ACM International Symposium on Low Power Electronics and Design, 2011

483 citations recorded by the source corpus.

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Analysis and characterization of inherent application resilience for approximate computing (2013, methodology): “Approximate computing has been applied to the design of hardware building blocks such as arithmetic units and entire datapaths, either through voltage overscaling [2, 3, 4] or through logic simplification [5, 6].”
A Survey of Techniques for Approximate Computing (2016, background): “Similarly, since the lower-order bits have smaller signiﬁcance than the higher-order bits, approximating them may have only a minor impact on QoR [Cho et al. 2014; Ganapathy et al. 2015; Ranjan et al. 2015; Sampson et al. 2013; Tian et al. 2015; Rahimi et al. 2015; Gupta et al. 2011].”
New Metrics for the Reliability of Approximate and Probabilistic Adders (2013, methodology): “01 V, respectively, for the three approximate implementations [8].”
Design and Analysis of Approximate Compressors for Multiplication (2015, methodology): “3 by an approximate full-adder cell (such as the first design proposed in [2]).”
Low-Power Digital Signal Processing Using Approximate Adders (2013, background): “A preliminary version of our work appeared in [22].”
Approximate Computing: A Survey (2016, methodology): “In [49], a transistor-level approximation is utilized to construct approximate adder cells.”