SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling

By Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, J. Hoe. 30th Annual International Symposium on Computer Architecture, 2003. Proceedings., 2003

652 citations recorded by the source corpus.

Current software-based microarchitecture simulators are many orders of magnitude slower than the hardware they simulate. Hence, most microarchitecture design studies draw their conclusions from drastically truncated benchmark simulations that are often inaccurate and misleading. We present the sampling microarchitecture simulation (SMARTS) framework as an approach to enable fast and accurate performance measurements of full-length benchmarks. SMARTS accelerates simulation by selectively measuring in detail only an appropriate benchmark subset. SMARTS prescribes a statistically sound procedure for configuring a systematic sampling simulation run to achieve a desired quantifiable confidence in estimates. Analysis of 41 of the 45 possible SPEC2K benchmark/ input combinations show CPI and energy per instruction (EPI) can be estimated to within 3% with 99.7% confidence by measuring fewer than 50 million instructions per benchmark. In practice, inaccuracy in micro-architectural state initialization introduces an additional uncertainty which we empirically bound to /spl sim/2% for the tested benchmarks. Our implementation of SMARTS achieves an actual average error of only 0.64% on CPI and 0.59% on EPI for the tested benchmarks, running with average speedups of 35 and 60 over detailed simulation of 8-way and 16-way out-of-order processors, respectively.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/d85973f1eab3646fc9d068bab824d174e564d3e3

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Citations in the corpus

Efficiently exploring architectural design spaces via predictive modeling (2006, background): “[40] model minimal instruction stream subsets in SMARTS to achieve results within desired confidence intervals.”
Benchmarking modern multiprocessors (2011, methodology): “To reduce the number of simulated instructions of a benchmark, a commonly used method is to take a subset of the instructions with statistical sampling, which requires a sophisticated mechanism in the simulator [17, 20, 80, 97].”
Victim replication: maximizing capacity while hiding wire delay in tiled chip multiprocessors (2005, methodology): “We extend the functional warming method for superscalars [26] to an SMP system, and fast-forward through periods of execution while maintaining cache and directory state [3].”
An Evaluation of High-Level Mechanistic Core Models (2014, methodology): “Validation against real hardware shows good accuracy, with an average single-core error of 11.1% and a maximum of 18.8% for the IW-centric model with a 1.5× slowdown compared to interval simulation.”
ZSim: fast and accurate microarchitectural simulation of thousand-core systems (2013, methodology): “Sampling: Robust statistical sampling [51, 53] and automated techniques to simulate a small, representative portion of execution [44] are also widely used to reduce simulation time of long-running workloads.”
Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation (2011, neutral): “These simulation points are chosen either randomly [7], periodically [31] or through phase analysis [26].”