Enhanced low-power high-speed adder for error-tolerant application

By Ning Zhu, W. Goh, G. Wang, Kiat Seng Yeo. International SoC Design Conference, 2009

311 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/d604e9764b21041ed734432c1662a9e2d01d610b

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Jie Han
2. Fabrizio Lombardi
3. Kaushik Roy
4. Anand Raghunathan
5. Jörg Henkel
6. Muhammad Akmal Shafique
7. Rehan Hafiz
8. Waqas Ahmad

In Hardware and Architecture

1. Kaushik Roy
2. Jörg Henkel
3. Fabrizio Lombardi
4. Muhammad Akmal Shafique
5. Anand Raghunathan
6. Jie Han

Citations in the corpus

• IMPACT: IMPrecise adders for low-power approximate computing (2011, background): “An errortolerant adder is proposed in [10] which operates by splitting the input operands into accurate and inaccurate parts.”
• New Metrics for the Reliability of Approximate and Probabilistic Adders (2013, background): “adder designs in [12] and [13] belong to the same category.”
• A low latency generic accuracy configurable adder (2015, methodology): “Table III provides a comparison of probability of error calculated by the formula and by running simulations on adder's different configurations.”
• Approximate computing: An emerging paradigm for energy-efficient design (2013, unknown): “METRICS FOR APPROXIMATE COMPUTING”