Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

By H. Mertens, R. Ritzenthaler, A. Hikavyy, M. Kim, Z. Tao, K. Wostyn, S. Chew, A. De Keersgieter, G. Mannaert, E. Rosseel and 18 more. 2016 IEEE Symposium on VLSI Technology, 2016

172 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/c120076a8559c8146ee1a3de06bad06a026eaa7c

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In Electrical and Electronic Engineering

1. Edward J. Nowak

Citations in the corpus

• Challenges and Limitations of CMOS Scaling for FinFET and Beyond Architectures (2019, methodology): “Cross-Sectional TEM images of staked NSFET and NWFET channels proposed by IBM/GLOBALFOUNDRIES/SAMSUNG Research Alliance Team (JDA) and IMEC respectively as future candidates for beyond FinFET technology nodes [38], [39], and [41].”
• Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates (2016, methodology): “In this context, we previously demonstrated GAA FETs based on vertically stacked 8-nm-diameter Si wires [3].”