Analog design in deep sub-micron CMOS

By K. Bult. Proceedings of the 26th European Solid-State Circuits Conference, 2000

140 citations recorded by the source corpus.

View Paper: https://www.semanticscholar.org/paper/b93fd1ef5b8a5a011854f79c237a6a2d4672e7b7

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

1. A. Annema
2. Bram Nauta
3. Peter R. Kinget
4. Christian C. Enz
5. S. Chatterjee
6. H. Tuinhout
7. Y. Tsividis
8. R. V. Langevelde

Citations in the corpus

• Device mismatch and tradeoffs in the design of analog circuits (2005, methodology): “We illustrate an analysis method for the calculation of the dc accuracy of large analog circuits based on a small signal analysis.”
• An MOS transistor model for RF IC design valid in all regions of operation (2002, methodology): “Fig. 3. CMOS process supply voltage scaling [ 17 ].”
• Analog circuits in ultra-deep-submicron CMOS (2005, methodology): “because larger capacitances have to be charged [15].”
• 0.5-V analog circuit techniques and their application in OTA and filter design (2005, background): “4, without affecting the overall gain of the circuit [14], [15], as long as where is the open-loop DC gain of the amplifier.”