Interconnect-power dissipation in a microprocessor

By Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum Shamir. International Workshop on System-Level Interconnect Prediction, 2004

496 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/b9091835ae309dda85156cd2375115c76f838d4b

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. A. Naeemi
2. James D. Meindl
3. H. Philip Wong
4. Bipul Chandra Paul
5. Daniele Ielmini
6. Shimeng Yu
7. Kaustav Banerjee
8. Hong Li

In Hardware and Architecture

1. H. Philip Wong

Citations in the corpus

• Performance Modeling for Single- and Multiwall Carbon Nanotubes as Signal and Power Interconnects in Gigascale Systems (2008, background): “Although individual local interconnects are short, their aggregate length is quite large, and their share in the delays of critical paths and power dissipation is large and growing [ 25 ], [26].”
• High-speed ultracompact buried heterostructure photonic-crystal laser with 13 fJ of energy consumed per bit transmitted (2010, unknown): “The energy used in transferring data must therefore be reduced, because over 50p of the total power is used by intra-chip interconnections, with this fraction becoming greater as the data rate increase”
• Fully Integrated Graphene and Carbon Nanotube Interconnects for Gigahertz High-Speed CMOS Electronics (2010, background): “for about 50% of the active processor power consumption [1],”