MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications

By H. Singh, Ming-Hau Lee, Guangming Lu, Fadi Kurdahi, N. Bagherzadeh, E. Filho. IEEE Trans. Computers, 2000

903 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/b43537e7736232523fee271cb32f7b9dcfc837e5

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. Christos Kozyrakis
2. Christina Delimitrou

In Electrical and Electronic Engineering

1. Christos Kozyrakis
2. Mark A. Horowitz
3. Jing Pu
4. Mingyu Gao
5. Xuan S. Yang
6. Joel S. Emer

In Hardware and Architecture

1. Mark A. Horowitz
2. Christos Kozyrakis

Citations in the corpus

• Reconfigurable computing: architectures and design methods (2005, methodology): “Actel ProASIC+ Fine 3-input block Horizontal and vertical 256x9 bit blocks Flash-based [3] tracks Altera Excalibur Fine 4-input Lookup Tables Horizontal and vertical 2Kbit memory blocks ARMv4T Embedded [5] tracks Processor Altera Stratix II Fine/Coarse 8-input Adaptive Horizontal and vertical 512 bi”
• ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix (2003, methodology): “Many coarse-grained architectures consist of a reconfigurable matrix and a relatively slow RISC processor, e.g., TinyRisc in MorphoSys [ 1 ] and ARC in Chameleon [3].”
• TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory (2017, background): “Recent NN accelerators are typically spatial architectures with a large number of processing elements (PEs) for multiply-accumulate (MAC) operations [10, 30, 42].”