ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix

By B. Mei, S. Vernalde, D. Verkest, H. Man, R. Lauwereins. International Conference on Field-Programmable Logic and Applications, 2003

622 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/a11bfb1db5bd877f5e32a7f23f64b0a68f8b2c9b

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. Christos Kozyrakis
2. Vivienne Sze
3. Joel S. Emer
4. Yu-hsin Chen
5. Christina Delimitrou

In Hardware and Architecture

1. Joel S. Emer
2. Mark A. Horowitz
3. Christos Kozyrakis
4. Vivienne Sze
5. Yu-hsin Chen

Citations in the corpus

• Reconfigurable computing: architectures and design methods (2005, methodology): “Actel ProASIC+ Fine 3-input block Horizontal and vertical 256x9 bit blocks Flash-based [3] tracks Altera Excalibur Fine 4-input Lookup Tables Horizontal and vertical 2Kbit memory blocks ARMv4T Embedded [5] tracks Processor Altera Stratix II Fine/Coarse 8-input Adaptive Horizontal and vertical 512 bi”
• Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks (2016, background): “SAs come in two flavors: coarse-grained SAs that consist of tiled arrays of ALU-style PEs connected together via on-chip networks [27] [28] [29], and fine-grained SAs that are usually in the form of an FPGA.”
• TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory (2017, background): “Recent NN accelerators are typically spatial architectures with a large number of processing elements (PEs) for multiply-accumulate (MAC) operations [10, 30, 42].”