The structural simulation toolkit
By A. Rodrigues, K. Hemmert, Brian W. Barrett, Chad D. Kersey, Ron A. Oldfield, M. Weston, R. Risen, J. Cook, Paul Rosenfeld, E. CooperBalls and 1 more. PERV, 2011
390 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/b397dc34ed94e8dd126a7351e5da60747611a389
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
- Bruce L. Jacob
- Elliott Cooper-Balis
- David A. Wood
- Tushar Krishna
- Pranith Kumar
- Lifeng Nai
- Hyesoon Kim
- Hyojong Kim
In Hardware and Architecture
- Bruce L. Jacob
- Elliott Cooper-Balis
- David A. Wood
- Tushar Krishna
- Pranith Kumar
- Lifeng Nai
- Hyesoon Kim
- Hyojong Kim
Citations in the corpus
- The gem5 Simulator: Version 20.0+ (2020, methodology): “For instance, gem5 has been integrated with the Structural Simulation Toolkit (SST) [36, 60], which uses gem5’s detailed CPU models in conjunction with SST’s multi-node modeling capabilities.”
- On the role of burst buffers in leadership-class storage systems (2012, background): “A number of universities and national laboratories have joined together to create the Structural Simulation Toolkit (SST) [35].”
- DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator (2020, positive): “DRAMsim3 can be integrated into popular CPU simulators or simulation frameworks such as SST [13], ZSim [15] and Gem5 [1] as their memory backend simulator.”
- Improving Performance via Mini-applications (2009, positive): “We used the Structural Simulation Toolkit [4] to simulate the inner loop for sparse matrix-vector multiplication.”
- DRAMSim2: A Cycle Accurate Memory System Simulator (2011, methodology): “Because the internals of the simulator are encapsulated into an interface that consists of just a few functions, it is easy to attach DRAMSim2 to any type of front end driver such as a trace reader, a cycle accurate CPU simulator such as MARSSx86 [4], or a discrete event simulation framework such as”
- GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks (2017, methodology): “We also thank Sandia National Labs for providing the SST/VaultSim framework.”