CacheBleed: a timing attack on OpenSSL constant-time RSA

By Yuval Yarom, Daniel Genkin, Nadia Heninger. Journal of Cryptographic Engineering, 2016

356 citations recorded by the source corpus.

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Translation Leak-aside Buffer: Defeating Cache Side-channel Protections with TLB Attacks (2018, background): “A number of previous efforts have observed that temporal information can be used to mount side-channel attacks over shared caches or similar ﬁne-grained channels [4, 15, 25, 38, 45, 61].”
Context-Sensitive Fencing: Securing Speculative Execution via Microcode Customization (2019, background): “mizations such as caches, branch speculation, memory disambiguation, and even DVFS, through side-channels such as memory bus activity [4], power consumption characteristics [8], branch access patterns [2, 29], faults [47, 40], acoustics [33, 32], electromagnetic effects [30], functional unit timing ”
A survey of microarchitectural timing attacks and countermeasures on contemporary hardware (2016, background): “[171] presented CacheBleed, a side-channel attack that exploits cache-bank collisions [54,77] to create measurable timing variations.”
HardFails: Insights into Software-Exploitable Hardware Bugs (2019, background): “The divide between hardware and software security research is starting to take its toll, as we witness increasingly sophisticated attacks that combine software and hardware bugs to exploit computing platforms at runtime [20, 23, 36, 43, 45, 64, 69, 72, 74].”