Translation Leak-aside Buffer: Defeating Cache Side-channel Protections with TLB Attacks

By Ben Gras, Kaveh Razavi, Herbert Bos, Cristiano Giuffrida. USENIX Security Symposium, 2018

365 citations recorded by the source corpus.

View Paper: https://www.semanticscholar.org/paper/d9a8a841d3e8d2c33b663d6f87bd3f8ec48bee1e

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

1. Ghada Dessouky
2. Mengjia Yan
3. David Gens
4. Julian Stecklina
5. Patrick Haney
6. Adam Morrison
7. Ahmad-Reza Sadeghi
8. Josep Torrellas

Citations in the corpus

• ZombieLoad: Cross-Privilege-Boundary Data Sampling (2019, background): “ttacker to observe the location of memory accesses. The granularity of the location observation depends on the spatial accuracy of the used side channel. Most common memory-based side-channel attacks [20, 22, 23, 25, 37, 56, 58, 71, 78, 79] have a granularity between one cache line [22, 23, 25, 79] ”
• InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy (2018, background): “Recent work has also shown side channels from cache coherence state changes [5] and data TLB state [18].”
• HardFails: Insights into Software-Exploitable Hardware Bugs (2019, background): “The divide between hardware and software security research is starting to take its toll, as we witness increasingly sophisticated attacks that combine software and hardware bugs to exploit computing platforms at runtime [20, 23, 36, 43, 45, 64, 69, 72, 74].”