FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates

By Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang, Jason Cong. IEEE Symposium on Field-Programmable Custom Computing Machines, 2017

299 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Computer Vision and Pattern Recognition

View Paper: https://www.semanticscholar.org/paper/88a00ce44e2a7f47aa1cc80b995addee3f21c266

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Citations in the corpus

Edge Computing for Autonomous Driving: Opportunities and Challenges (2019, background): “We have seen much recent progress on acceleration localization and perception functions, with many studies focused on reconfigurable fabrics [44]–[48]; however, with limited chip area, it is inefficient to integrate one accelerator for each perception and localization task.”
DNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs (2018, methodology): “More frameworks are proposed to automatically map DNNs onto FPGAs using RTL [11, 12] or RTL-HLS templates [13].”
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, unknown): “…[35], FPGA-Exploration [36], OpenCL-FPGA-CNN [37] [126], Caffeine [38], DeepBurning [39], FPGA-DPCNN [40], TABLA [41], DNNWEAVER [42], FP-DNN [43], FPGA-LSTM [44], ESE [45], FPGA-Dataﬂow [46], FPGA-BNN [47], FPGA-Utilization [48], FFT-CNN [49], VIBNN [50], iSwitch [127], Shortcut-Mining…”
Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs (2020, methodology): “Our performance is less than [45] and [46], this mainly comes from two aspects.”
A survey of FPGA-based accelerators for convolutional neural networks (2018, background): “multiple months for an expert HW designer [22].”
FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review (2019, methodology): “FP-DNN [171] is an end-to-end framework that automatically generates optimized FPGA-based implementa-”
The Deep Learning Compiler: A Comprehensive Survey (2020, methodology): “parameters are usually determined by the design space exploration using various strategies, such as combining the performance model and auto-tuning. DNN Weaver [82], AngelEye [41], ALAMO [67], FP-DNN [40], SysArrayAccel [100] are typical FPGA DL code generator targeting the processor architecture. W”
CompAct (2019, background): “Similarly, since SAs are highly efficient for matrix multiplications, prior work [12, 22] has advocated for its use in hardware acceleration as well.”