Efficient memory integrity verification and encryption for secure processors
By G. Suh, Dwaine E. Clarke, Blaise Gassend, Marten van Dijk, Srini Devadas. Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36., 2003
305 citations recorded by the source corpus.
Subfields: Artificial Intelligence, Electrical and Electronic Engineering, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/838e638434b94f23bda308f51172e57d2780e302
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Artificial Intelligence
- Srini Devadas
- Charles W. O'Donnell
- G. Suh
- Ruby B. Lee
- Victor Costan
- Ilia A. Lebedev
- Thomas Eisenbarth
- Gorka Irazoqui Apecechea
In Electrical and Electronic Engineering
- Srini Devadas
- Charles W. O'Donnell
- G. Suh
- Roel Maes
- Patrick Schaumont
- Abhranil Maiti
- Farinaz Koushanfar
- Said F. Al-Sarawi
In Hardware and Architecture
- Srini Devadas
- Charles W. O'Donnell
- G. Suh
- Ruby B. Lee
- Zhenghong Wang
- Jeffrey S. Dwoskin
- Roel Maes
- Patrick Schaumont
Citations in the corpus
- Architecture for protecting critical secrets in microprocessors (2005, background): “In addition, memory replay attacks can be prevented using known memory authentication systems, e.g., [10] [ 34 ].”
- Aegis: A Single-Chip Secure Processor (2007, methodology): “For memory encryption, Aegis encrypts and decrypts all off-chip data transfers in the ME regions using a one-time-pad, or countermode, encryption scheme.(11) Figure 5 shows how an evicted cache block is sent through XOR logic with an AES encryption of its memory address, a time stamp, and some const”