Low-Power CMOS VLSI Circuit Design

By Kaushik Roy, S. Prasad. 2000

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Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits (2003, background): “To minimize SCEs, a sufficiently large aspect ratio (AR) of the device is required [41].”
Energy dissipation and transport in nanoscale devices (2010, background): “However, an understanding of transient heat conduction is necessary for short duration pulsed operation, such as during digital switching [9] or electrostatic discharge (ESD) events [96].”
Charge-pump circuits: power-consumption optimization (2002, background): “Indeed, there ensues a reduction in speed and noise margins in digital circuits [ 5 ], [6], a reduction of dynamic range in analog circuits [4], and additionally, difficulties arise in allowing read and write operations to take place in memories [7].”