Multi-gate SOI MOSFETs

By Jean-Pierre Colinge. 2007

274 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/7e8c707acf14fc9f19d5c58f8628b4f1c3ce47f1

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Uwe Schroeder
2. Thomas Mikolajick
3. I. Fina
4. Vincent Garcia
5. J. MacManus‐Driscoll
6. M. Lira-Cantú
7. B. Dkhil
8. G. Niklasson

Citations in the corpus

• Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node (2017, background): “By contrast, gate-all-around nanowire transistors (NW-FETs) are expected to further enable device scaling due to their better short-channel control as well as high current density [7], [8].”
• Towards Oxide Electronics: a Roadmap (2019, background): “A device is free of short-channel effects if the effective gate length of a MOSFET is larger than 5–10 times the natural length [396,397] This require-ment clearly indicates that a thin channel (SOI), multiple gates, and high dielectric constant materials allow scaling avoiding SCE.”