The SpiNNaker Project
By S. Furber, Francesco Galluppi, Steve Temple, Luis A. Plana. Proceedings of the IEEE, 2014
1,303 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering, Mechanical Engineering
View Paper: https://www.semanticscholar.org/paper/28ba0ed8526e4322d81602a1da21b2b43fbe9b10
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Electrical and Electronic Engineering
- Michael Pfeiffer
- Thomas Pfeil
- Kaushik Roy
- Shih-Chii Liu
- Giacomo Indiveri
- Garrick Orchard
- Hesham Mostafa
- Matthew Cook
In Mechanical Engineering
- Shimeng Yu
- Michael Pfeiffer
- Garrick Orchard
- Sumit Bam Shrestha
- Thomas Pfeil
- Giacomo Indiveri
- Wei Dang Lu
- Andrew J. Davison
Citations in the corpus
- A Survey of Neuromorphic Computing and Neural Networks in Hardware (2017, background): “to achieve a certain motion [67]–[69], [361], [663], [1082], [1083], [1261], [1279], [1527], [1784], [1885], [2550], [2551], social learning [2552], [2553], and target or wall following [498], [606], [1576], [1682], [2554]. Thus far, in terms of robotics, the most common use of neuromorphic implemen”
- Memory and Information Processing in Neuromorphic Systems (2015, background): “…as faithfully as possible the equations and specifications provided by the neuro-scientists), and bandwidth requirements (e.g., to speed up the simulations by two or three orders of magnitude, or to guarantee that all transmitted signals reach their destinations within some clock cycle duration).”
- HOTS: A Hierarchy of Event-Based Time-Surfaces for Pattern Recognition (2017, methodology): “This can allow most of the processing to be parallelized to be implemented on platforms such as FPGAs or new, highly parallel, computer architectures such as SpiNNaker [36].”
- Deep Rewiring: Training very sparse deep networks (2017, background): “…hardware, where either hard upper bounds on network connectivity are unavoidable (Schemmel et al., 2010; Merolla et al., 2014) or fast on-chip memory of local processing cores is severely limited, for example the 96 MByte lo-cal memory of cores in the SpiNNaker system (Furber et al., 2014).”
- Conversion of Continuous-Valued Deep Networks to Efficient Event-Driven Networks for Image Classification (2017, methodology): “Multi-layered spiking networks have been implemented on digital commodity platforms such as FPGAs (Neil and Liu, 2014; Gokhale et al., 2014), but spiking networks with more than tens of thousands of neurons can be implemented on large-scale neuromorphic spiking platforms such as TrueNorth (Benjamin ”
- Opportunities for neuromorphic computing algorithms and applications (2022, background): “This has been successfully accomplished across a variety of large-scale neuromorphic hardware systems, including SpiNNaker 5,6 and Loihi 7 .”
- Training Spiking Neural Networks Using Lessons From Deep Learning (2021, methodology): “From the engineer’s perspective, neuron models derived from experimental results have allowed us to design extremely energy-efficient networks when running on hardware tailored to SNNs [219], [220], [221], [222], [223], [224], [225].”
- Fast-classifying, high-accuracy spiking deep networks through weight and threshold balancing (2015, background): “This has been driven both by the interest to build more biologically realistic neural network models, and by recent improvements and the availability of larger-scale neuromorphic computing platforms, which are optimized for emulating brain-like spike-based computation in dedicated analog or digital ”
- A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses (2015, background): “…processing cores with dedicated memory structures and communication schemes optimized for spiking neural networks architectures (Wang et al., 2013; Furber et al., 2014; Neil and Liu, 2014), or full-custom digital circuit solutions that implement large arrays of spiking neurons with programmable…”
- Deep Learning With Spiking Neurons: Opportunities and Challenges (2018, methodology): “…event representation (AER) protocol (Mahowald, 1994; Boahen, 2000), which is used to connect, e.g., event-based sensors (Lichtsteiner et al., 2008) via digital interconnect to neuromorphic chips (Indiveri et al., 2011; Amir et al., 2017) or digital post-processing hardware (Furber et al., 2014).”