An energy-efficient charge recycling approach for a SAR converter with capacitive DAC

By Brian P. Ginsburg, Anantha P. Chandrakasan. 2005 IEEE International Symposium on Circuits and Systems, 2005

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A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$W at 1 MS/s (2010, methodology): “The DAC is not fully binary weighted but uses a split-capacitor array for better efficiency [6].”
A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC (2008, background): “For some further energy reduction the DACs are not completely binary weighted, but use a split capacitor bank [2].”
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS (2010, background): “The power dissipation is just derived from what is needed to drive the bottom-plate parasitic of the capacitive arrays, while in the conventional charge-redistribution [13], [22] and the charge-recycling [14] methods the necessary MSB “up” transition costs significant switching energy and settling t”
V CM -based monotonic capacitor switching scheme for SAR ADC (2013, background): “Compared to conventional architecture [1], the set and down [2], V CM -based [3], and new tri-level switching scheme [4] reduces the switching energy by 81.26, 87.54, and 96.89%, respectively.”
500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC (2007, methodology): “[23] analyzes three alternatives to the conventional capacitor array and switching procedure.”