A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

By Yan Zhu, Chi-Hang Chan, U. Chio, Sai-Weng Sin, S. U, R. Martins, F. Maloberti. IEEE Journal of Solid-State Circuits, 2010

718 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/1188db091e80f5fec1ad4d509b88f4173bde4913

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1. Yu Xiao
2. Zhangming Zhu
3. Xiaoli Song

Citations in the corpus

• V CM -based monotonic capacitor switching scheme for SAR ADC (2013, background): “Compared to conventional architecture [1], the set and down [2], V CM -based [3], and new tri-level switching scheme [4] reduces the switching energy by 81.26, 87.54, and 96.89%, respectively.”
• Deep Underground Neutrino Experiment (DUNE), Far Detector Technical Design Report, Volume II: DUNE Physics (2020, neutral): “20) with a split-cap DAC based on Vcm switching [57], and has the option to be calibrated for offset compensation.”