A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC
By Michiel van Elzakker, Ed van Tuijl, Paul F. J. Geraedts, Daniël Schinkel, Eric A. M. Klumperink, Bram Nauta. IEEE International Solid-State Circuits Conference, 2008
303 citations recorded by the source corpus.
Subfields: Artificial Intelligence, Biomedical Engineering, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/3a89926cc6f7b735e05e264df5d3bd36211ed3c2
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Citations in the corpus
- A 26 $\mu$ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios (2011, background): “5, a two-stage dynamic comparator is used [5].”
- A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS (2010, background): “The speed of a SAR ADC is determined by the time required by the DAC to settle within 1/2-LSB.”
- A/D converter trends: Power dissipation, scaling and digitally assisted architectures (2008, background): “A well-know example of an architecture that achieves very high efficiency is the chargebased successive approximation register (SAR) converter [1, 9, 28].”