Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication

By Gang Huang, M. Bakir, A. Naeemi, H. Chen, James D. Meindl. 2007 IEEE Electrical Performance of Electronic Packaging, 2007

147 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/76a7eb88857b3e61725388e60989af10a3a7cd87

How researchers see this paper

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In Electrical and Electronic Engineering

1. Hong Li
2. Chuan Xu
3. Kaustav Banerjee
4. Roberto Suaya
5. Navin Srivastava

Citations in the corpus

• Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs (2010, background): “The power/ground TSVs and horizontal wires are usually periodically placed, forming the power/ground grid [35].”