Realizing biological spiking network models in a configurable wafer-scale hardware system

By J. Fieres, Johannes Schemmel, K. Meier. 2008

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Finding a roadmap to achieve large neuromorphic hardware systems (2013, methodology): “Other resulting systems, such as Neurogrid (Lin et al., 2006; Silver et al., 2007) and Wafer level implementations from the group centered in Heidelberg (Schemmel et al., 2008a,b) in best cases get close to the analog VMM efﬁciency, typical of an ANN.”
STDP and STDP variations with memristors for spiking neuromorphic learning systems (2013, methodology): “The latter yields an additive type of STDP, while the former results in a quadratic type STDP. Note that a memristor can be either voltage/ﬂux or current/charge driven, independently of whether it is a “wall” or a “ﬁlament” memristor.”
Artificial neural networks in hardware: A survey of two decades of progress (2010, unknown): “on wafer-scale integration of large SNN models [262,263].”
A Survey of Neuromorphic Computing and Neural Networks in Hardware (2017, unknown): “[17]–[19], [99], [100], [323], [324], [326]–[329], [331]–[333],”