STDP and STDP variations with memristors for spiking neuromorphic learning systems

By T. Serrano‐Gotarredona, Timothée Masquelier, T. Prodromakis, Giacomo Indiveri, B. Linares‐Barranco. Frontiers in Neuroscience, 2013

489 citations recorded by the source corpus.

In this paper we review several ways of realizing asynchronous Spike-Timing-Dependent-Plasticity (STDP) using memristors as synapses. Our focus is on how to use individual memristors to implement synaptic weight multiplications, in a way such that it is not necessary to (a) introduce global synchronization and (b) to separate memristor learning phases from memristor performing phases. In the approaches described, neurons fire spikes asynchronously when they wish and memristive synapses perform computation and learn at their own pace, as it happens in biological neural systems. We distinguish between two different memristor physics, depending on whether they respond to the original “moving wall” or to the “filament creation and annihilation” models. Independent of the memristor physics, we discuss two different types of STDP rules that can be implemented with memristors: either the pure timing-based rule that takes into account the arrival time of the spikes from the pre- and the post-synaptic neurons, or a hybrid rule that takes into account only the timing of pre-synaptic spikes and the membrane potential and other state variables of the post-synaptic neuron. We show how to implement these rules in cross-bar architectures that comprise massive arrays of memristors, and we discuss applications for artificial vision.

Subfields: Cellular and Molecular Neuroscience, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/4471777be500f83da2b430f0010ecb574a3f46bf

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In Cellular and Molecular Neuroscience

In Electrical and Electronic Engineering

Citations in the corpus

Memory and Information Processing in Neuromorphic Systems (2015, background): “Several proposals have been made for leveraging basic nanoscale RRAM attributes in synapse circuits in neuromorphic architectures [15], [18], [92], [143]; many of these proposals do not use these devices as conventional RAM cells, but distribute them within and across the synapse circuits in the neu”
STDP-based spiking deep neural networks for object recognition (2016, background): “biological hardware, simulations could run several order of magnitude faster than real time [47].”
Event-driven contrastive divergence for spiking neuromorphic systems (2013, methodology): “This may be impractical due to the very large number of synapse circuits in the network, but may be less problematic when using Resistive RandomAccess Memorys (RRAMs) (also called memristors) crossbar arrays to emulate synapses [12, 34, 51].”