A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

By L. Kull, T. Toifl, M. Schmatz, P. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, T. Andersen, Y. Leblebici. IEEE Journal of Solid-State Circuits, 2013

322 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/69cd11bf39f5cf9007bb0b97789bb21963dee69d

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. J. Joshua Yang
2. John Paul Strachan
3. R. S. Williams
4. Huaqiang Wu
5. Bin Gao
6. He Qian
7. Ali Shafiee
8. Miao Hu

Citations in the corpus

• Fully hardware-implemented memristor convolutional neural network (2020, methodology): “The parameters associated with the other peripheral circuitry blocks are extracted using the simulated circuits at the 65-nm technology node, except for the S & H block 40 and the 8-bit ADC block 41 .”
• ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars (2016, background): “12 mm [36]).”
• Hardware implementation of memristor-based artificial neural networks (2024, unknown): “Therefore, not only the system becomes more sensitive and error-prone, but also its power consumption increases exponentially as the resolution of DACs and ADCs increase 163,164 .”