Dynamic-sleep transistor and body bias for active leakage power control of microprocessors

By J. Tschanz, S. Narendra, Y. Ye, B. Bloechel, Shekhar Y. Borkar, V. De. 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., 2003

318 citations recorded by the source corpus.

View Paper: https://www.semanticscholar.org/paper/695a5f0efb934aad8c22b327df9e054ee05a31c6

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

1. T. Karnik
2. S. Narendra
3. V. De
4. A. Keshavarzi
5. Massimo Alioto
6. Shekhar Y. Borkar

Citations in the corpus

• Parameter variations and impact on circuits and microarchitecture (2003, background): “It was shown empirically that 450mV is the optimal FBB for sub-9Onm generations at high temperature [ 7 ].”
• Thousand Core ChipsA Technology Perspective (2007, background): “Thus you need only two supply voltages, two sleep transistors [2] in each core to select a supply vol tage, and a frequency divider in each core to select the freque ncy of operation.”
• An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS (2008, unknown): “9(a)], sleep transistor and body bias circuits [15] are used to reduce active and standby leakage power, which are controlled at full-chip, tile-slice, and individual tile levels based on workload.”