A Hardware Design Language for Timing-Sensitive Information-Flow Security

By Danfeng Zhang, Yao Wang, G. Suh, A. Myers. 2015

256 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Electrical and Electronic Engineering, Hardware and Architecture, Privacy & Security

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Citations in the corpus

Asleep at the Keyboard? Assessing the Security of GitHub Copilot’s Code Contributions (2021, neutral): “Tools like SecVerilog [29] and SecChisel [30], have limited support for security properties and do not directly deal with CWEs.”
HardFails: Insights into Software-Exploitable Hardware Bugs (2019, methodology): “SecVerilog [22, 75] overcomes this by extending the Verilog language with a dynamic security type system.”
SecChisel Framework for Security Verification of Secure Processor Architectures (2019, methodology): “Both SecVerilog [23] and Caisson [14] use information flow tracking (IFT) to enforce security properties at compile time, but SecChisel is the first to be based on the Chisel language.”
Hardware Penetration Testing Knocks Your SoCs Off (2020, background): “[2] extended Hardware Penetration Testing Knocks Your SoCs Off”
This Paper Is Included in the Proceedings of the 12th Usenix Symposium on Operating Systems Design and Implementation (osdi '16). Ryoan: a Distributed Sandbox for Untrusted Computation on Secret Data Ryoan: a Distributed Sandbox for Untrusted Computation on Secret Data (unknown): “Systems that track information flow down to the hardware gate level [53, 83, 84, 98] form a basis for strong information flow guarantees, and close timing and cache channels ignored by Ryoan.”
A Formal Foundation for Secure Remote Execution of Enclaves (2017, methodology): “Recent examples for hardware design are [37, 38, 75].”
An Empirical Cybersecurity Evaluation of GitHub Copilot's Code Contributions (2021, background): “Tools like SecVerilog [28] and SecChisel [29], meanwhile, have limited support for security properties and do not directly deal with CWEs.”
Formal Abstractions for Attested Execution Secure Processors (2017, background): “in the formal methods community [31, 57, 58, 73], that can potentially allow us to ensure that the actual secure processor implementation meets the specification.”