DAG-aware AIG rewriting: a fresh look at combinational logic synthesis

By Alan Mishchenko, S. Chatterjee, Robert K. Brayton. 2006 43rd ACM/IEEE Design Automation Conference, 2006

583 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/548daadbe6b14fdeb73fda48639e048fee51c852

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Armando Solar-Lezama
2. Rastislav Bodík
3. Alan Mishchenko
4. Robert K. Brayton

In Hardware and Architecture

1. Armando Solar-Lezama
2. Rastislav Bodík
3. Alan Mishchenko
4. Robert K. Brayton
5. Sanjit A. Seshia
6. Rishabh Singh
7. Rajeev Alur

Citations in the corpus

• Program sketching (2012, methodology): “For the last 10 iterations we switched our SAT solver to ABC [11] because it provides much better performance for hard SAT problems.”
• ABC: An Academic Industrial-Strength Verification Tool (2010, methodology): “Combinational synthesis using AIG rewriting [26].”
• Combinatorial sketching for finite programs (2006, methodology): “For the hardest problems we ve encountered, ABC provides order of magnitude improvement over the standard SAT solver.”
• Program synthesis by sketching (2008, methodology): “For all these benchmarks the synthesizer used ABC [49] as the solution engine because we have found it to work better on stencil problems.”
• LegUp: high-level synthesis for FPGA-based processor/accelerator systems (2011, methodology): “Such segments are disassembled from the software binary to a higher-level representation, which is then synthesized to hardware [9].”