LegUp: high-level synthesis for FPGA-based processor/accelerator systems

By Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski. Symposium on Field Programmable Gate Arrays, 2011

613 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/2fb9660e25df30a61803f33b74d37021288afe14

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. Aiman H. El-Maleh
2. Sadiq M. Sait
3. Ahmad Shawahna

In Hardware and Architecture

1. Aiman H. El-Maleh
2. Sadiq M. Sait
3. Ahmad Shawahna

Citations in the corpus

• FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review (2019, methodology): “The availability of high-level synthesis (HLS) tools, using C or C++, from FPGA vendors lowers the programming hurdle and shortens the development time of FPGA-based hardware accelerators [68]–[70].”
• A Survey and Evaluation of FPGA High-Level Synthesis Tools (2016, neutral): “LEGUP [9] is a research compiler developed at the University of Toronto, first released in 2011 and currently on its forth public release.”
• Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs (2020, background): “More importantly, high level synthesis (HLS) using C or C ++ has greatly lowered the programming hurdle of FPGAs and improve the productivity [25]–[27].”