ABC: An Academic Industrial-Strength Verification Tool
By Robert K. Brayton, Alan Mishchenko. International Conference on Computer Aided Verification, 2010
1,058 citations recorded by the source corpus.
ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs ABC combines scalable logic transformations based on And-Inverter Graphs (AIGs), with a variety of innovative algorithms A focus on the synergy of sequential synthesis and sequential verification leads to improvements in both domains This paper introduces ABC, motivates its development, and illustrates its use in formal verification.
Subfields: Computational Theory and Mathematics, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/1c1ee7b39616c52e96d91e243dc8996cfed11027
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In Computational Theory and Mathematics
In Hardware and Architecture
- Muhammad Yasin
- Yier Jin
- David Zhigang Pan
- Zheng Zhao
- Meng Li
- Kaveh Shamsi
- Travis Meade
- Ozgur Sinanoglu
Citations in the corpus
- Provably-Secure Logic Locking: From Theory To Practice (2017, methodology): “Our current SFLL implementation relies on the existing securityagnostic tools such as Synopsys DC Compiler and ABC [6] for synthesis.”
- Machine Learning for Electronic Design Automation: A Survey (2021, methodology): “There are many logic transformations in current synthesis tools such as ABC [14].”
- AppSAT: Approximately deobfuscating integrated circuits (2017, methodology): “We used ABC [23] to synthesize randomly generated truth-tables resulting in circuits with 200-300 gates, and then obfuscated them using fault based XOR/XNOR [11] and MUX [11] obfuscation, clique based XOR/XNOR [12] obfuscation, and random XOR/XNOR obfuscation [2] using [4].”