Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

By Ioannis Savidis, Eby G. Friedman. IEEE Transactions on Electron Devices, 2009

210 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/4e8e59b00c89c3588c7c5e41ff477b0788f6a64f

How researchers see this paper

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In Electrical and Electronic Engineering

1. Hong Li
2. Chuan Xu
3. Kaustav Banerjee
4. Roberto Suaya
5. Navin Srivastava

Citations in the corpus

• Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs (2010, background): “In [12] and [13], the depletion region model simply ignores the interface charge.”