High-Level Synthesis for FPGAs: From Prototyping to Deployment

By Jason Cong, B. Liu, S. Neuendorffer, J. Noguera, Kees A. Vissers, Zhiru Zhang. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011

839 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/4b11ed4f8af982d21434c3574009287bbfac3a9d

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. Rajesh K. Gupta
2. Chris Dick
3. Mani B. Srivastava
4. Christoph Studer
5. Guohui Wang
6. Zhiru Zhang
7. Sajal K. Das
8. Deborah Estrin

In Hardware and Architecture

1. Mani B. Srivastava
2. Christoph Studer
3. Guohui Wang
4. Tom Goldstein

Citations in the corpus

• Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs (2017, methodology): “We make use of Xilinx SDSoC 2016.1 as the primary design tool, which leverages Vivado HLS and Vivado to perform the actual HLS compilation and FPGA implementation.”
• Large-Scale MIMO Detection for 3GPP LTE: Algorithms and FPGA Implementations (2014, methodology): “A host of FPGA designs for linear data detection in conventional (small-scale) MIMO systems have been proposed in the literature [28]–[30], [40]–[44].”
• A Survey and Evaluation of FPGA High-Level Synthesis Tools (2016, methodology): “Vivado HLS [43], formerly AutoPilot [44], was developed initially by AutoESL until it was acquired by Xilinx in 2011.”