Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs

By Ritchie Zhao, Weinan Song, Wentao Zhang, Tianwei Xing, Jeng-Hau Lin, Mani B. Srivastava, Rajesh K. Gupta, Zhiru Zhang. Symposium on Field Programmable Gate Arrays, 2017

416 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/95355936980ff7aa401c59265f1475c78999f788

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Vision and Pattern Recognition

1. Kurt Keutzer
2. Xianglong Liu
3. Bichen Wu
4. Nicu Sebe
5. Jingkuan Song
6. Dacheng Tao
7. Qijing Huang
8. Raja Giryes

In Electrical and Electronic Engineering

1. Kurt Keutzer
2. Bichen Wu
3. Tailin Liang
4. Sarangapani Jagannathan
5. C. John Glossner
6. G. Suh
7. Kees A. Vissers
8. Vipul Kumar Mishra

Citations in the corpus

• Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating (2019, methodology): “Similar to several other CNN accelerators [16–18], we add a specialized line buffer between the window buffers and the global feature buffer to further exploit the data locality and reuse of the feature maps.”
• NICE: Noise Injection and Clamping Estimation for Neural Network Quantization (2018, methodology): “…complex scheduling and data movement, FPGA-based inference accelerators has been described as heterogeneous system using OpenCL (Wang et al., 2016a;b; Aydonat et al., 2017) or as standalone accelerator using HLS compilers (Ghaffari & Sharifian, 2016; Umuroglu et al., 2017; Zhao et al., 2017).”
• Pruning and Quantization for Deep Neural Network Acceleration: A Survey (2021, methodology): “Because FPGAs operate at the gate level, they are often used in low-bit and binary neural networks [168, 256, 187].”
• A comprehensive survey on model compression and acceleration (2020, methodology): “In another research, Zhao et al. (2017) presented the binarized NN accelerator synthesized for FPGA based implementation.”
• Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs (2018, methodology): “[37] [38] run the BNN on a smaller device ZC7020.”
• AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, neutral): “…[36], OpenCL-FPGA-CNN [37] [126], Caffeine [38], DeepBurning [39], FPGA-DPCNN [40], TABLA [41], DNNWEAVER [42], FP-DNN [43], FPGA-LSTM [44], ESE [45], FPGA-Dataflow [46], FPGA-BNN [47], FPGA-Utilization [48], FFT-CNN [49], VIBNN [50], iSwitch [127], Shortcut-Mining [128], FA3C [129], E-RNN [130]”
• Binary Neural Networks: A Survey (2020, methodology): “Both [101] and [102] from Xilinx also studied the FPGA-based binary network accelerator using different strategies.”
• I Know What You See: Power Side-Channel Attack on Convolutional Neural Network Accelerators (2018, methodology): “For the CNN accelerator [39], we set the line size of the line buer to 28, input channel to 1 and the kernel size to 3⇥3”
• FINN-R (2018, neutral): “[70] CNV-X Zedboard 143 94† ∼ 46, 900† 207.”