Demonstration of subthrehold swing smaller than 60mV/decade in Fe-FET with P(VDF-TrFE)/SiO2 gate stack

By Giovanni A. Salvatore, D. Bouvet, Adrian M. Ionescu. 2008 IEEE International Electron Devices Meeting, 2008

137 citations recorded by the source corpus.

This work experimentally demonstrates, for the first time, that by integrating a thin ferroelectric layer into a gate stack of a standard MOS transistor one, it is possible to overcome the 60 mV/decade subthreshold swing limit at room temperature of MOSFET. We find sub-threshold swings as low as 13 mV/decade in Fe-FETs with 40 nm P(VDF-TrFE)/SiO2 gate stack. The mechanism governing the low subthreshold swing in Fe-FET transistors is the negative capacitance of the ferroelectric layer that provides voltage amplification; with our particular ferroelectric gate stack we report for the first time negative capacitance at room temperature.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/47ba78e2d87634761c5fce030b1ca2eb7792f09a

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Citations in the corpus

• Steep Slope and Near Non-Hysteresis of FETs With Antiferroelectric-Like HfZrO for Low-Power Electronics (2015, background): “The polymer FE was studied and integrated for a <60mV/decade swing [3], [4] for low-power operation applications.”