A 12 b 75 MS/s pipelined ADC using open-loop residue amplification
By Boris Murmann, Bernhard E. Boser. 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., 2003
559 citations recorded by the source corpus.
Subfields: Biomedical Engineering, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/4733504a9b6de40a5914d78dcac26da960b9b9ed
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In Biomedical Engineering
In Electrical and Electronic Engineering
Citations in the corpus
- A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue (2008, background): “A coarse–fine ADC improves resolution by amplifying the residue between the input and closest coarse level, then quantizing the amplified residue again with the same coarse resolution.”
- A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS (2006, background): “While it is possible to make use of open-loop residue amplification [9], an extra calibration loop is needed, increasing overall complexity and power consumption.”
- A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS (2010, unknown): “Recent works [5]–[9] opti-”