Challenges, developments and applications of silicon deep reactive ion etching

By F. Laermer, A. Urban. 2003

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Geometric optimization of a micro heat sink with liquid flow (2006, methodology): “These channels were produced using silicon-based MEMS technology to create microchannels within silicon wafers that had trapezoidal or triangular cross-sections (anisotropic wet etching on wafers) or rectangular cross-sections (DRIE or wet etching on wafers) as opposed to more traditional circular c”
Direct Liquid Jet-Impingment Cooling With Micron-Sized Nozzle Array and Distributed Return Architecture (2006, background): “With current methods to structure silicon with a feature width m 10 µm and a feature depth as large as the wafer thickness, new architectures of cold plates are accessible for high-volume manufacturing at low cost, e.g. arrays with more than 10,000 nozzles [ 11 ].”
A practical implementation of silicon microchannel coolers for high power chips (2005, methodology): “f-a pp * R e Continuous 60 um pitch (2)”
The Piezoresistive Effect of SiC for MEMS Sensors at High Temperatures: A Review (2015, background): “However, as the etching rate of SiC is very low (100 nm to 1 μm/min [127], [128]) in comparison to that of Si (10 μm/min [129]), laser micro-machining and wafer drilling/milling are employed to reduce the etching time of”