Last-Level Cache Side-Channel Attacks are Practical

By Fangfei Liu, Yuval Yarom, Qian Ge, Gernot Heiser, Ruby B. Lee. IEEE Symposium on Security and Privacy, 2015

1,236 citations recorded by the source corpus.

We present an effective implementation of the Prime+Probe side-channel attack against the last-level cache. We measure the capacity of the covert channel the attack creates and demonstrate a cross-core, cross-VM attack on multiple versions of GnuPG. Our technique achieves a high attack resolution without relying on weaknesses in the OS or virtual machine monitor or on sharing memory between attacker and victim.

Subfields: Artificial Intelligence, Signal Processing

View Paper: https://www.semanticscholar.org/paper/452676284bc053201f26e94cfc35e97ca2735a3b

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Citations in the corpus

High-Resolution Side Channels for Untrusted Operating Systems (2017, methodology): “The prime-and-probe technique has been used in synchronous [36] and asynchronous attacks [30,33], targeting the L1 cache [37] and well as the LLC [30, 33].”
A Systematic Evaluation of Transient Execution Attacks and Defenses (2018, background): “Cache attack senders can be implemented in very little code [57, 61, 24], for instance via “tmp = array[secret_byte * 4096];”, i.”
DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks (2015, background): “to be effective in a multitude of settings, such as crossVM key-recovery attacks [9, 12, 20, 30], including attacks across cores [5, 14, 16, 28].”
Detecting Privileged Side-Channel Attacks in Shielded Execution with Déjà Vu (2017, background): “, [58, 55, 24, 33]), non-root userspace processes (e.”
Inferring Fine-grained Control Flow Inside SGX Enclaves with Branch Shadowing (2016, background): “Further, the attack recovered 66% of the private key bits by running the decryption only once, unlike existing cachetiming attacks, which usually demand several hundreds to several tens of thousands of iterations [20, 35, 65].”
Meltdown: Reading Kernel Memory from User Space (2018, methodology): “Several cache attack techniques have been proposed and demonstrated in the past, including Prime+Probe [16] and Flush+Reload [23].”
SgxPectre: Stealing Intel Secrets from SGX Enclaves Via Speculative Execution (2018, background): “iming difference between cache hits and cache misses to infer the victim’s memoryaccesspatterns. TypicalexamplesofcachesidechannelattacksarePRIME-PROBE andFLUSH-RELOAD attacks. In PRIME-PROBE attacks [54, 53, 84, 51, 7, 68, 46, 36], by pre-loading cache lines in a cache set, the adversary expects th”
BranchScope: A New Side-Channel Attack on Directional Branch Predictor (2018, background): “All but the first attack (which is a timing-analysis attack) rely on filling the BTB (which is a cache-like structure) and thus are similar to the cache side-channel attacks [38, 56].”
Flip Feng Shui: Hammering a Needle in the Software Stack (2016, background): “Much recent work [11, 12, 29, 40, 58] shows that benign kernel optimizations such as transparent huge pages, vsyscall pages, and memory deduplication can become dangerous tools in the hands of a capable attacker.”
S$A: A Shared Cache Attack That Works across Cores and Defies VM Sandboxing -- and Its Application to AES (2015, background): “Therefore, using huge pages makes it possible to reach a higher resolution Prime+Probe style attack.”
Intel SGX Explained (2016, background): “and would only be vulnerable to more sophisticated attacks that target the shared LLC, such as [131, 196].”
Cache Telepathy: Leveraging Shared Resource Attacks to Learn DNN Architectures (2018, background): “Flush+Reload [17] and Prime+Probe [18] are two powerful cache-base side channel attacks.”
Oblivious Multi-Party Machine Learning on Trusted Processors (2016, methodology): “While we rely on the processor to guarantee that only the machine learning code inside the enclave has direct access to the data, achieving privacy still requires a careful selection, adaptation, and implementation of machine-learning algorithms, in order to prevent the exploitation of any side chan”
Sanctum: Minimal Hardware Extensions for Strong Software Isolation (2016, background): “While early attacks required access to the victim’s CPU core, recent sophisticated attacks [39, 61] target the last-level cache (LLC), which is shared by all cores in a socket.”
The Spy in the Sandbox - Practical Cache Attacks in Javascript (2015, methodology): “2Mbps bandwidth achieved by the native code cross-VM covert channel implemented by [23].”
T-SGX: Eradicating Controlled-Channel Attacks Against Enclave Programs (2017, background): “However, this mitigation is not enough to cope with asynchronous cache timing attacks that use the last-level cache (LLC) [28, 39].”
Spectre Attacks: Exploiting Speculative Execution (2018, methodology): “Attacks of the latter type include microarchitectural attacks exploiting cache timing [8, 30, 48, 52, 55, 69, 74], branch prediction history [1, 2], branch target buffers [14, 44] or open DRAM rows [56].”
ZombieLoad: Cross-Privilege-Boundary Data Sampling (2019, methodology): “So far, all cross-VM covert channels either relied on Prime+Probe [46, 50, 51, 59, 77], DRAMA [58], or bus locking [76].”
Packet Chasing: Spying on Network Packets over a Cache Side-Channel (2019, neutral): “This allows us to spot various errors that might happen during the transmission including bit loss, multiple insertion of bits, or bit swaps [24].”
CacheZoom: How SGX Amplifies The Power of Cache Attacks (2017, methodology): “…lap-top with Intel(R) Skylake Core(TM) i7-6500U processor Even though Skylake processors use an adaptive LRU cache replacement policy and the adaptive behavior is undocumented [23], our results show that we can still use the pointer chasing eviction set technique [36] to detect memory accesses.”