A/D converter trends: Power dissipation, scaling and digitally assisted architectures

By Boris Murmann. IEEE Custom Integrated Circuits Conference, 2008

311 citations recorded by the source corpus.

How researchers see this paper

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RedEye: Analog ConvNet Image Sensor Architecture for Continuous Mobile Vision (2016, background): “That is, energy consumption of analog circuits can be reduced by allowing a higher noise level [10], [11].”
Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors (2012, methodology): “In subsequent analysis, the FOM used to show tradeoffs is 100 fJ/conversion step, which is consistent with the general performance of modern ADCs over a wide range of resolutions and sampling speeds [22].”
The Race for the Extra Decibel: A Brief Review of Current ADC Performance Trajectories (2015, background): “Recently, however, we have seen that moderate- to high-resolution converters tend to follow a power quadrupling per effective bit, a trade-off that is consistent with noise-limited analog circuits [9].”
A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$W at 1 MS/s (2010, unknown): “energy efficiency [2].”