Integration of nanoscale memristor synapses in neuromorphic computing architectures

By Giacomo Indiveri, B. Linares‐Barranco, Robert A. Legenstein, George Deligeorgis, T. Prodromakis. Nanotechnology, 2013

592 citations recorded by the source corpus.

Conventional neuro-computing architectures and artificial neural networks have often been developed with no or loose connections to neuroscience. As a consequence, they have largely ignored key features of biological neural processing systems, such as their extremely low-power consumption features or their ability to carry out robust and efficient computation using massively parallel arrays of limited precision, highly variable, and unreliable components. Recent developments in nano-technologies are making available extremely compact and low power, but also variable and unreliable solid-state devices that can potentially extend the offerings of availing CMOS technologies. In particular, memristors are regarded as a promising solution for modeling key features of biological synapses due to their nanoscale dimensions, their capacity to store multiple bits of information per element and the low energy required to write distinct states. In this paper, we first review the neuro- and neuromorphic computing approaches that can best exploit the properties of memristor and scale devices, and then propose a novel hybrid memristor-CMOS neuromorphic circuit which represents a radical departure from conventional neuro-computing approaches, as it uses memristors to directly emulate the biophysics and temporal dynamics of real synapses. We point out the differences between the use of memristors in conventional neuro-computing architectures and the hybrid memristor-CMOS circuit proposed, and argue how this circuit represents an ideal building block for implementing brain-inspired probabilistic computing paradigms that are robust to variability and fault tolerant by design.

Subfields: Cellular and Molecular Neuroscience, Cognitive Neuroscience, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/fe818b111417e2be0deed1d2e9dad5d0f44eb24f

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In Cellular and Molecular Neuroscience

In Cognitive Neuroscience

In Electrical and Electronic Engineering

Citations in the corpus

On the Robustness of a Neural Network (2017, unknown): “Recent progress in neuromorphic hardware brings such a solution, going beyond the Von Neumann paradigm (relying on logical circuits) and using electronic chips that are themselves neural networks [10], [11], [9], [12].”
A Survey of Neuromorphic Computing and Neural Networks in Hardware (2017, methodology): “tion (depending on the type of network) [862]–[868], [1025]–[1027], [1036], [1063]–[1065], [1103], [1149]–[1154], [1177], [1178], [1200], [1206]–[1208], [1262]–[1264], [1284], [1356], [1357], [1456], [1803]–[1820]. Sometimes the memristor is simply used as a synaptic weight storage element. In other”
Memory and Information Processing in Neuromorphic Systems (2015, methodology): “Several proposals have been made for leveraging basic nanoscale RRAM attributes in synapse circuits in neuromorphic architectures [15], [18], [92], [143]; many of these proposals do not use these devices as conventional RAM cells, but distribute them within and across the synapse circuits in the neu”
Efficient and self-adaptive in-situ learning in multilayer memristor neural networks (2018, background): “ith the introduction of hardware accelerators 1 – 4 for inference in deep neural networks (DNNs) 5 – 9 , the focus on improving overall energy and time performance arti ﬁ cial intelligence applications is now on training.”
On-chip photonic synapse (2017, background): “As a first and key step to the construction of neuromorphic architecture, it is essential to develop suitably plastic synapse-like devices (1, 9, 10)—not least because synapses are by far the most numerous component of real brains, outnumbering neurons by several orders of magnitude (2).”