Evaluating the Hardware Performance of a Million-Bit Multiplier

By Yarkin Doröz, Erdinç Öztürk, Berk Sunar. 2013

40 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Electrical and Electronic Engineering, Hardware and Architecture

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Citations in the corpus

HEAX: An Architecture for Computing on Encrypted Data (2019, background): “ation. A line of research focuses on designing very large integer multipliers (768K-bit to 1.18M-bit multiplications) – based on FPGAs or ASICs – that can be used to accelerate homomorphic operations [13, 28, 29, 61, 62]. In [14], a large-integer multiplier and a Barrett modular reduction are propos”
A Survey on Homomorphic Encryption Schemes (2017, background): “Therefore, there are works focusing particularly on this problem using the customized ASICs [Doröz et al. 2013; Wang et al. 2014; Doröz et al. 2015a].”
Accelerating Somewhat Homomorphic Evaluation using FPGAs (2015, background): “ASIC NTT modmul [17] GH-FHE 90nm TSMC 2.”
Accelerating integer-based fully homomorphic encryption using Comba multiplication (2014, methodology): “Architectures targeting Application Speciﬁc Integrated Circuit (ASIC) technology have also been proposed to improve the performance of FHE schemes [17], [18].”
Accelerating Homomorphic Evaluation on Reconfigurable Hardware (2015, background): “These may be reasons that previous work mainly focuses on using GPUs [19,40,41] and ASICs [21,44], and that FPGA implementations either work only with small parameters and on-chip memory [11] or explicitly do not take into account the complexity of transferring data between an FPGA and a host [9,35]”
Accelerating LTV Based Homomorphic Encryption in Reconfigurable Hardware (2015, background): “Therefore, a good number of works focused on developing FFT/NTT based large integer multipliers [17,18,35,35].”
High-Speed Fully Homomorphic Encryption Over the Integers (2014, methodology): “More recently, an ASIC implementation of a multiplier for the GH FHE scheme is proposed by Doröz et al [18]; this implementation shows comparable performance to the original software implementation and uses less area.”
Accelerating NTRU based homomorphic encryption using GPUs (2014, methodology): “To tackle the efficiency bottleneck the use of alternative platforms, such as GPUs [16], reconfigurable logic [17]–[21] and custom ASIC [22], [23] has been proposed.”
Modular Hardware Architecture for Somewhat Homomorphic Function Evaluation (2015, background): “Dor¨oz et al. [18] presented a million-bit multiplier for the GH scheme on ASIC.”
HEAX: High-Performance Architecture for Computation on Homomorphically Encrypted Data in the Cloud (2019, background): “A line of research focuses on designing very large integer multipliers – based on FPGAs or ASICs – that can be used to accelerate homomorphic operations [74, 75, 28, 29, 13].”
HEPCloud: An FPGA-Based Multicore Processor for FV Somewhat Homomorphic Function Evaluation (2018, background): “Hence, it is not surprising that during the recent years several publications [8], [13], [14], [15], [26], [28], [31], [33], [40], [41] have reported re-sults on hardware-based acceleration of different FHE and SHE schemes or their central operations.”