High-Speed Fully Homomorphic Encryption Over the Integers

By Xiaolin Cao, Ciara Moore, Máire O’neill, Neil Hanley, Elizabeth O'Sullivan. 2014

43 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Information Systems

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Citations in the corpus

HEAX: An Architecture for Computing on Encrypted Data (2019, methodology): “…customized hardware for non-CKKS schemes have taken one of these approaches: (i) Designing co-processors that only accelerate certain low-level ring operations [14, 19, 20, 30, 39, 61]; high-level operations are performed on the CPU-side, which makes the co-processors of limited practical use.”
A Survey on Homomorphic Encryption Schemes (2017, background): “Such a large and reconfigurable environment provided by FPGAs motivates many researchers to speed up the practicality of FHE schemes (Cousins et al. 2012; Wang and Huang 2013; Cao et al. 2013; Moore et al. 2013; Chen et al. 2015; Cao et al. 2014; Moore et al. 2014a; Cousins et al. 2014; Roy et al. 2”
Accelerating Homomorphic Evaluation on Reconfigurable Hardware (2015, methodology): “These may be reasons that previous work mainly focuses on using GPUs [19,40,41] and ASICs [21,44], and that FPGA implementations either work only with small parameters and on-chip memory [11] or explicitly do not take into account the complexity of transferring data between an FPGA and a host [9,35]”
HEAX: High-Performance Architecture for Computation on Homomorphically Encrypted Data in the Cloud (2019, background): “In [14], a large-integer multiplier and a Barrett modular reduction are proposed that can accelerate HE operations by 11×.”
Modular Hardware Architecture for Somewhat Homomorphic Function Evaluation (2015, background): “The same researchers later presented the ﬁrst implementation of the full FHE encryption in [10].”
Accelerating integer-based fully homomorphic encryption using Comba multiplication (2014, methodology): “Previously, Cao et al. proposed the ﬁrst hardware implementation [16] of the encryption step of an FHE scheme over the integers [11], speciﬁcally investigating the use of a Virtex-7 FPGA platform.”