Modular Hardware Architecture for Somewhat Homomorphic Function Evaluation

By Sujoy Sinha Roy, Kimmo U. Järvinen, Frederik Vercauteren, Vassil S. Dimitrov, Ingrid M. R. Verbauwhede. 2015

47 citations recorded by the source corpus.

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In Artificial Intelligence

Citations in the corpus

HEAX: An Architecture for Computing on Encrypted Data (2019, background): “mance of YASHE [10] and LTV [45] schemes or their variants. These constructions – based on an overstretched NTRU assumption – are subject to a subfield lattice attack [3] and are no longer secure. In [52], an architecture for YASHE scheme is proposed that provides 25×performance improvement over CPU”
Accelerating Homomorphic Evaluation on Reconfigurable Hardware (2015, methodology): “These may be reasons that previous work mainly focuses on using GPUs [19,40,41] and ASICs [21,44], and that FPGA implementations either work only with small parameters and on-chip memory [11] or explicitly do not take into account the complexity of transferring data between an FPGA and a host [9,35]”
HEPCloud: An FPGA-Based Multicore Processor for FV Somewhat Homomorphic Function Evaluation (2018, methodology): “Hence, it is not surprising that during the recent years several publications [8], [13], [14], [15], [26], [28], [31], [33], [40], [41] have reported results”
A High-Speed Accelerator for Homomorphic Encryption using the Karatsuba Algorithm (2017, background): “To our knowledge, only [14] and [15] provide complete accelerators with batching, although the former focuses on the server side only and the latter only targets complex homomorphic algorithms.”
HEAX: High-Performance Architecture for Computation on Homomorphically Encrypted Data in the Cloud (2019, methodology): “In [65], an architecture for YASHE scheme is proposed that provides 25× performance improvement over CPU.”
A Full RNS Variant of FV Like Somewhat Homomorphic Encryption Schemes (2016, background): “[23] for such kind of implementation on FPGA).”