Dot-product engine for neuromorphic computing: Programming 1T1M crossbar to accelerate matrix-vector multiplication

By Miao Hu, John Paul Strachan, Zhiyong Li, Emmanuelle Merced Grafals, N. Dávila, Catherine E. Graves, Sity Lam, Ning Ge, R. S. Williams, Jianhua Yang and 1 more. Design Automation Conference, 2016

686 citations recorded by the source corpus.

Subfields: Cellular and Molecular Neuroscience, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/2fdaa46ed54c593f8558dd90857cc5cadbabfa30

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In Cellular and Molecular Neuroscience

In Electrical and Electronic Engineering

Citations in the corpus

Parallel convolutional processing using an integrated photonic tensor core (2021, background): “Moreover, they are plagued by the same limitations of electronic addressing 20 , with additional challenges in the manufacturing and implementation due to issues with device variability 21,22 , cyclability 23 and drift 24,25 .”
Hardware implementation of memristor-based artificial neural networks (2024, neutral): “The weight update process is implemented by applying voltage or current pulses to the memristors (block 13 and 14), following the Write-Verify (or Close Loop Tunning) 194 – 196 , or the Write-without-Verify (or Open Loop Tunning) 103,107,197,198 .”
A Survey of Neuromorphic Computing and Neural Networks in Hardware (2017, neutral): “[1796], [1797], [1800], [1801], [1818], [1827], [1829], [1831],”
Recent Advances in Convolutional Neural Network Acceleration (2018, methodology): “For ASIC design, despite of using methods in structure level such as block-circulant projection in Section 4.1.3 and SC in Section 4.2, to improve the design in implementation level, memory can be expanded and locality can be increased to reduce data transporting within systems for deep neural netwo”
Neuro-Inspired Computing With Emerging Nonvolatile Memorys (2018, methodology): “[99] developed a 64 × 64 TiOx-based 1T1R array with 6-b (64 levels) offline training and a single-layer perceptron for MNIST image recognition.”
PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning (2017, methodology): “For example, [1] used 6-bit ReRAM cells and [43] used 5 bits.”
The future of electronics based on memristive systems (2018, methodology): “The finite wiring resistance of the metal lines connecting the memory cells poses another challenge during read and write 18 .”