The State-of-the-Art in IC Reverse Engineering

By R. Torrance, D. James. Workshop on Cryptographic Hardware and Embedded Systems, 2009

369 citations recorded by the source corpus.

How researchers see this paper

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Evaluating the security of logic encryption algorithms (2015, background): “The gate-level netlist can be reverse-engineered from this [22].”
Physically Unclonable Functions (2012, methodology): “as demonstrated by Tarnovsky [140], Torrance and James [143].”
PUFKY: A Fully Functional PUF-Based Cryptographic Key Generator (2012, background): “Moreover, even high-level physical protection mechanisms are often not sufficient to prevent well-equipped and motivated adversaries from discovering stored secrets [24, 25].”
Verifiable ASICs (2016, background): “” However, such testing of large, complex ICs with billions of nanometer sized transistors is expensive, error prone, and “stretches analytical capabilities to the limits” [110].”
Security analysis of integrated circuit camouflaging (2013, methodology): “Reverse engineering of an IC to extract a gate-level netlist by performing the various steps shown in Figure 2 has been demostrated in [2,25].”
Breakthrough Silicon Scanning Discovers Backdoor in Military Chip (2012, background): “Keywords: Hardware Assurance; silicon scanning; side-channel analysis; hardware Trojans and backdoors”
Fault Injection Attacks on Cryptographic Devices: Theory, Practice, and Countermeasures (2012, background): “For instance, [38] reports a successful reconstruction of an entire read bus of a memory containing a cryptographic key without damaging the contents of the memory.”