Delay variability: sources, impacts and trends

By S. Nassif. 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056), 2000

234 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Mechanical Engineering

View Paper: https://www.semanticscholar.org/paper/238de3a78baa66b590c077ae95b33570b0ee2fc2

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. David T. Blaauw
2. Hongliang Chang
3. Sachin S. Sapatnekar

In Mechanical Engineering

1. Hongliang Chang
2. Sachin S. Sapatnekar

Citations in the corpus

• Statistical timing analysis considering spatial correlations using a single PERT-like traversal (2003, methodology): “The process parameters and their max percentages of deviations from the nominal values (Table 1) used here are based on predictions from [13, 14].”
• Statistical timing analysis for intra-die process variations with spatial correlations (2003, background): “In our analysis, we focus on gate length variability since it has been shown to have a dominant impact on gate delay [1].”