Energy-driven integrated hardware-software optimizations using SimplePower

By Narayanan Vijaykrishnan, Mahmut Taylan Kandemir, M. J. Irwin, Hyun Suk Kim, W. Ye. Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201), 2000

336 citations recorded by the source corpus.

With the emergence of a plethora of embedded and portable applications, energy dissipation has joined throughput, area, and accuracy/precision as a major design constraint. Thus, designers must be concerned with both optimizing and estimating the energy consumption of circuits, architectures, and software. Most of the research in energy optimization and/or estimation has focused on single components of the system and has not looked across the interacting spectrum of the hardware and software. The novelty of our new energy estimation framework, SimplePower, is that it evaluates the energy considering the system as a whole rather than just as a sum of parts, and that it concurrently supports both compiler and architectural experimentation. We present the design and use of the SimplePower framework that includes a transition-sensitive, cycle-accurate datapath energy model that interfaces with analytical and transition sensitive energy models for the memory and bus subsystems, respectively. We analyzed the energy consumption of ten codes from the multidimensional array domain, a domain that is important for embedded video and signal processing systems, after applying different compiler and architectural optimizations. Our experiments demonstrate that early estimates from the SimplePower energy estimation framework can help identify the system energy hotspots and enable architects and compiler designers to focus their efforts on these areas.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/236fd3287ca2c55c5db3f018ba0612bf2922924a

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Citations in the corpus

Run-time power estimation in high performance microprocessors (2001, background): “Architectural level power simulators [5][19] have made signi cant strides toward de-mystifying power dissipation in more complex processors.”
Load balancing and unbalancing for power and performance in cluster-based systems (2001, neutral): “[3 3, 16, 18]), for the memory (e.g. [22, 32 ]), for the disk (e.g.”
A static power model for architects (2000, background): “Several researchers have reported modifying performance simulators to provide power estimates as well [6, 35].”
Data Center Energy Consumption Modeling: A Survey (2016, methodology): “In another additive power model, over all energy usage of the memory system is modeled as [187],”
Full-System Power Analysis and Modeling for Server Environments (2006, background): “Current approaches to power modeling fall into two broad classes: measurements of power at the hardware level [8], [1 3], [11] or modeling of power at the simulation level [5], [7], [9 ], [14], [22], [26], [27], [29].”