Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

By H. Yang, R. Malik, S. Narasimha, Ying Li, R. Divakaruni, P. Agnello, S. Allen, A. Antreasyan, J. Arnold, K. Bandy and 69 more. IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004., 2004

154 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/01759d9d4eb8808f35f5c7b8a22c3da10cce09f8

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1. S. Thompson

Citations in the corpus

• Uniaxial-process-induced strained-Si: extending the CMOS roadmap (2006, background): “compressive capping layers) [5] are also being widely adopted”