5nm-gate nanowire FinFET
By Fu-Liang Yang, Di-Hong Lee, Hou-Yu Chen, Chang-Yun Chang, Sheng-Da Liu, Cheng-Chuan Huang, Tang-Xuan Chung, Hung-Wei Chen, Chien-Chao Huang, Yi-Hsuan Liu and 16 more. Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 2004
235 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/fb3ea615e90447b413f220b9f2e694ba2cd0aa4f
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In Electrical and Electronic Engineering
Citations in the corpus
- High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices (2006, background): “, relaxed body thickness yet gaining similar short-channel control as thin-body double-sided FinFET [7], [8], excellent transconductance [12], and drain-induced bar-”
- Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires (2006, unknown): “108-109, 2002 [2] Fu-Liang Yang et al.”