Memristor crossbar arrays with 6-nm half-pitch and 2-nm critical dimension
By Shuang Pi, Can Li, Hao Jiang, W. Xia, H. Xin, J. Joshua Yang, Qiangfei Xia. Nature Nanotechnology, 2018
444 citations recorded by the source corpus.
The memristor1,2 is a promising building block for next-generation non-volatile memory3, artificial neural networks4–7 and bio-inspired computing systems8,9. Organizing small memristors into high-density crossbar arrays is critical to meet the ever-growing demands in high-capacity and low-energy consumption, but this is challenging because of difficulties in making highly ordered conductive nanoelectrodes. Carbon nanotubes, graphene nanoribbons and dopant nanowires have potential as electrodes for discrete nanodevices10–14, but unfortunately these are difficult to pack into ordered arrays. Transfer printing, on the other hand, is effective in generating dense electrode arrays15 but has yet to prove suitable for making fully random accessible crossbars. All the aforementioned electrodes have dramatically increased resistance at the nanoscale16–18, imposing a significant barrier to their adoption in operational circuits. Here we demonstrate memristor crossbar arrays with a 2-nm feature size and a single-layer density up to 4.5 terabits per square inch, comparable to the information density achieved using three-dimensional stacking in state-of-the-art 64-layer and multilevel 3D-NAND flash memory19. Memristors in the arrays switch with tens of nanoamperes electric current with nonlinear behaviour. The densely packed crossbar arrays of individually accessible, extremely small functional memristors provide a power-efficient solution for information storage and processing.A nanofin structure enables a working memristor array with 2-nm feature size and 4.5-Tbit per square inch packing density.
Subfields: Cellular and Molecular Neuroscience, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/eb185843f718cd3e09fe330239da62b45bfeaeb4
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In Cellular and Molecular Neuroscience
In Electrical and Electronic Engineering
Citations in the corpus
- Power-efficient combinatorial optimization using intrinsic noise in memristor Hopfield neural networks (2020, background): “Memristors have shown size scalability 53 to 2 nm and fast operations 54 well below 1 ns. Augmenting digital technology with increasingly energy-efficient analogue components further extends analogue scaling with the potential to continue even after the end of Moore’s law, should future…”
- Memristive technologies for data storage, computation, encryption, and radio-frequency communication (2022, background): “Academic groups have published observations of the memristive effect in even smaller structures with lateral sizes down to 2 nm (25) and even in one single atom (26), but in such reports the endurance was always very limited (<100 cycles), the yield was low (<50%), and the variability was high (not ”
- Fully hardware-implemented memristor convolutional neural network (2020, methodology): “The associated expenditure of chip area could be minimized in the future by employing high-density integration of memristors 32,33 .”
- Neuro-inspired computing chips (2020, background): “NVM devices also have the potential to be scaled down to sub-2-nm size 42 and integrated into ultrahigh-density three-dimensional (3D) array 43 , as well as the capability to emulate bio-plausible behaviors 44 .”